ĭSP Builder interfaces the industry-leading system-level design software Simulink from The MathWorks with Altera's Quartus II design software. Simulink and MATLAB are available today from The MathWorks at. SOPC Builder version 2.6 is now integrated with Altera's Quartus® II version 2.1 design software, with subscription pricing of $1,995, including 12 months of software upgrades.
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The DSP Builder tool is available for download for a free 30-day evaluation from Altera's DSP Solutions Center at. Subscription pricing for Altera's DSP Builder version 2.0 is $1,995 and includes 12 months of software upgrades. More information on the new C-code-based DSP design flow can be found on the Altera web site at Īltera's complete C-code-based DSP design flow is supported now in DSP Builder version 2.0 and SOPC Builder version 2.6. For example, a FIR filter that executes in one cycle on an FPGA can take up to 20 cycles on a digital signal processor. Using IP cores as hardware accelerators instead of generic multiply-accumulators (MACs) allows algorithms to be executed up to 20 times faster. "Altera is providing customers with the broadest and most cost-effective solutions based on Stratix™ devices, the highly successful Nios processor, and parameterizable DSP IP cores."
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"For software engineers who have traditionally used 'C' code to implement their DSP designs with processors, using a familiar C-code-based design flow to target FPGAs is a big advantage," said Justin Cowling, Altera's director of intellectual property marketing. This complete system-on-a-programmable-chip (SOPC) design flow is handled seamlessly by Altera's SOPC Builder tool, including the integration of memory, communications peripherals, and processor busses. Altera's comprehensive portfolio of more than 60 DSP intellectual property (IP) cores can be used as function calls for the Nios processor. A key feature of this new flow is the support of 'C' function calls for DSP hardware accelerators, designed at the system level using The MathWorks' Simulink and Altera's DSP Builder tools. "The combined capabilities of Altera's DSP Builder and SOPC Builder tools offer significant benefits to the entire DSP development community, allowing designers to use programmable logic for a wider range of DSP applications."Īltera provides users with industry-standard software development tools such as the GNUPro compiler and debugger, an open-source C/C++ development tool suite optimized for the Altera® Nios® embedded processor. "By offering the programmable logic industry's first C-code-based design flow for DSP development, Altera opens the doors to a broad range of DSP designers who wouldn't otherwise use FPGAs," said Ahmed Shihab, technical director at Alcahest, a design consultancy active in the development of DSP systems. This flow allows DSP software engineers to target programmable logic devices (PLDs), without having to learn hardware description language (HDL), thereby reducing the overall system cost and number of devices on their board. San Jose, Calif., Septem-Altera Corporation (NASDAQ: ALTR) today announced the availability of the FPGA industry's first C-code-based design flow for digital signal processing (DSP) systems. New Tool Flow Delivers the Benefits of Reconfigurable DSP Solutions to Designers of DSP Systems
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